library ieee;
 use ieee.std_logic_1164.all;
 
 entity T_FF1 is
      port( R,T  : in std_logic;
            Q,QB : out std_logic);
 end T_FF1;
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 architecture RTL of T_FF1 is
      signal NODE : std_logic;
 begin
      Q <= NODE;
      QB <= not NODE;
      process(R,T)
      begin
           if (R = '0')then
                NODE <= '0';
           elsif (T 'event and T ='1')then
                NODE <= not NODE;
           end if;
      end process;
 end RTL;